Month: March 2013

Hello world DE0-Nano with VHDL

Here i will be explaining how to write a very simple VHDL code to simulate an And gate with two inputs. In the following post I have mentioned about device families, pin assignments, compilation and programming the actual hardware. I will not repeat those information please go through this post if you have not.

Only difference here is that instead of adding Block diagram / Schematic to the project you should select File >New > VHDL file. Then you will get a window to type the code.

Following is the VHDL code,

entity VHDLturo is
port (A, B:in BIT;
Z : out BIT);
end VHDLturo;


architecture logicfunc of VHDLturo is
begin
Z <= A and B;
end architecture logicfunc;

(more…)

Hello world DE0-Nano

Last few weeks i have been going through lots of books on FPGAs and VHDL. Now it is the time to write the first VHDL program. But before even writing a VHDL program I decided to draw a simple schematic design and power it up through the DE0-Nano.

First you need to start QuartusII and start a new project. Select Cyclone IV E device family and EP4CE22F17C6 device. That is the hardware you have in the DE0-Nano. After you created the project, just go to File > New. Then select Block diagram / Schematic file.

Now you will see the window where you should draw the design. Click on schadd icon. Then type ‘and2’ in the Name text box. Now you can draw and gates in the design by simply clicking on it. For time being just include one And gate.

and2

(more…)

Testing and Configuring the Altera DE0 Nano FPGA

$(KGrHqV,!k8E+rCZTg-JBQDE4nujG!~~60_35Altera DE0 Nano contains a very good software/tool which actually is a control panel. It gives you an easy platform to make sure that the Development board is functioning properly. This blog post will have details on configuring the control panel and installing USB blaster drivers.
(more…)