D-flip flip with Set and Reset

Following is the VHDL code for the design of a D-Flip flop with asynchronous set and reset functions. Normally Set and Reset is used to determine the initial state of a Flip flop in order to prevent it starting off with some arbitrary state.

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
begin
p0: process (Clock,Reset,Set) is
variable state: std_logic;
begin
	if (Reset = '0') then
	state := '0';
	elsif (Set = '0') then
	state := '1';
	elsif rising_edge(CLock) then
	state := D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

The same can be done using a signal instead of a variable as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
signal state: std_logic;
begin
p0: process (Clock,Reset,Set) is
begin
	if (Reset = '0') then
	state <= '0';
	elsif (Set = '0') then
	state <= '1';
	elsif rising_edge(CLock) then
	state <= D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

Make sure you do the pin assignment correctly.

2

Thank you.

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