DE0-Nano

7 segment up counter for DE0-Nano

In my previous post I have mentioned about the 7-segment display that I soldered for my DE0-Nano board. Now it’s time to get a simple program going in it. Here I will be implementing a up counter in the FPGA fabric. Conventional truth tables and karnaugh maps have been used to derive the logic for this simple task. Also in this demo you will understand how to develop a design module by module and how to combine them together using VHDL.

LED-7-Segment-Display
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D-flip flip with Set and Reset

Following is the VHDL code for the design of a D-Flip flop with asynchronous set and reset functions. Normally Set and Reset is used to determine the initial state of a Flip flop in order to prevent it starting off with some arbitrary state.

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
begin
p0: process (Clock,Reset,Set) is
variable state: std_logic;
begin
	if (Reset = '0') then
	state := '0';
	elsif (Set = '0') then
	state := '1';
	elsif rising_edge(CLock) then
	state := D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

The same can be done using a signal instead of a variable as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
signal state: std_logic;
begin
p0: process (Clock,Reset,Set) is
begin
	if (Reset = '0') then
	state <= '0';
	elsif (Set = '0') then
	state <= '1';
	elsif rising_edge(CLock) then
	state <= D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

Make sure you do the pin assignment correctly.

2

Thank you.

Programming a D-flip flop in VHDL

Following are few ways to code a positively edge triggered D Flip Flop in VHDL.

Method 1:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process (Clock) is
begin
if (Clock = '1') then
Q <= D;
Qbar <= not D;
end if;
end process p0;
end architecture dff_arch;

Method 2:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process is
begin
wait until (CLock = '1');
Q <= D;
Qbar <= not D;
end process p0;
end architecture dff_arch;

Method 3:( The most correct design)

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is 
begin

p0: process (Clock) is
variable state: std_logic;
begin

if rising_edge(Clock) then
state := D;
end if;
Q <= state;
Qbar <= not state;
end process p0; end architecture dff_arch;

Pin configuration is as follows:

1

Thank you.

Configuring DE0-Nano EPCS64 flash device.

Similar to most of the FPGA devices available in the market today, the DE0-Nano also uses SRAM cells to store the configuration data it requires to operate correctly. Since SRAM is a volatile memory it will lose all the data once we power down the device. So whenever we power up the device it will read the configuration data from some other non-volatile memory element and reprogram the FPGA fabric.

DE0-Nano has a flash device named as EPCS64. It has 64Mbits capacity. This blog post will teach you how to program the EPCS64 flash device so that you can save your program in the chip indefinitely (theoretically).

  • Generate the .sof file by compiling your program.
  • Goto File > Convert Programming Files
  • Under ‘output programming file’, select ‘JTAG indirect configuration file’ as the programming file type.’
  • Select ‘EPCS64’ as the configuration device.
  • Give a file name and path.
  • Under ‘Input files to convert’ click on ‘Flash loader’.
  • Then click on ‘Add device’ button at the right side of the window.
  • Select ‘EP4CE22’ under ‘Cyclone IV E’ and click ‘ok’.
  • Under ‘Input files to convert’ click on ‘SOF data’.
  • Then click on ‘Add file’ button at the right side of the window.
  • Select you generated ‘.sof’ file which is generally it is located in the ‘output_files’ folder.
  • Finally click on generate button.

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Simple bit-shift example in VHDL

Here is another simple VHDL code to carryout simple bit shifting operation. I decided to post simple VHDL codes in this blog so that any newbie who reads this will be able to find some examples to work on. Make sure that you assign correct pins for inputs and outputs as mentioned in the

https://unboxnbeyond.wordpress.com/2013/03/24/hello-world-de0-nano-with-vhdl/#more-143

‘A’ should be connected to a push button
‘B’ should be connected to LEDs.

VHDL code:

library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;

entity bitshiftror is
port (A: in std_logic;
		B: out std_logic_vector(7 downto 0));
end entity bitshiftror;

architecture bitshiftor of bitshiftror is

signal B_out: BIT_VECTOR(7 downto 0) := (0 => '1', others => '0');
constant n: NATURAL := 1;

begin
aa: process (A) is
begin
	if((A xor '1') = '1') then
		B_out <= (B_out ror n);

		B <= to_stdlogicvector(B_out);				
	end if;
end process aa;
end architecture bitshiftor;

Thank you.

Hello world DE0-Nano with VHDL

Here i will be explaining how to write a very simple VHDL code to simulate an And gate with two inputs. In the following post I have mentioned about device families, pin assignments, compilation and programming the actual hardware. I will not repeat those information please go through this post if you have not.

Only difference here is that instead of adding Block diagram / Schematic to the project you should select File >New > VHDL file. Then you will get a window to type the code.

Following is the VHDL code,

entity VHDLturo is
port (A, B:in BIT;
Z : out BIT);
end VHDLturo;


architecture logicfunc of VHDLturo is
begin
Z <= A and B;
end architecture logicfunc;

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Hello world DE0-Nano

Last few weeks i have been going through lots of books on FPGAs and VHDL. Now it is the time to write the first VHDL program. But before even writing a VHDL program I decided to draw a simple schematic design and power it up through the DE0-Nano.

First you need to start QuartusII and start a new project. Select Cyclone IV E device family and EP4CE22F17C6 device. That is the hardware you have in the DE0-Nano. After you created the project, just go to File > New. Then select Block diagram / Schematic file.

Now you will see the window where you should draw the design. Click on schadd icon. Then type ‘and2’ in the Name text box. Now you can draw and gates in the design by simply clicking on it. For time being just include one And gate.

and2

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Testing and Configuring the Altera DE0 Nano FPGA

$(KGrHqV,!k8E+rCZTg-JBQDE4nujG!~~60_35Altera DE0 Nano contains a very good software/tool which actually is a control panel. It gives you an easy platform to make sure that the Development board is functioning properly. This blog post will have details on configuring the control panel and installing USB blaster drivers.
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FPGA starter kit comparison (BASYS2 or DE0-Nano)

The next device I am going to purchase is an FPGA development board. Since I am a newbie to FPGAs I wanted to buy a simple board to start my experiments on it. There are lots of FPGA boards available in e-bay for less cost. I don’t know why but my guts kept telling me to go for a board from a respected company and directly from them. So I did it. The money i could spare on these is 120$ max.

I searched for chips by the leading manufacturers of FPGAs, Xilinx and Altera. Then I found that Digilent and Terasic offers two entry level FPGA development boards, the BASYS2 and the DE0-Nano respectively; for chips by Xilinx and Altera respectively. Both these have an academic pricing (which i am entitled to) of 59$ and with shipping it will cost around 100$. In-fact BASYS2 with 250K gates (will explain later) 119$ and DE0-Nano is 112$.

First let’s look at the two boards as shown in their website,

Altera DE0-Nano is one on the left and the Basys™2 Spartan-3E is the one on the right.

de0_nano

BASYS2-top-400

To me the Digilent Basys2 looks better than DE0-Nano. It has all those gadgets in the board which makes it look better.

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