D flip flop

Programming a D-flip flop in VHDL

Following are few ways to code a positively edge triggered D Flip Flop in VHDL.

Method 1:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process (Clock) is
begin
if (Clock = '1') then
Q <= D;
Qbar <= not D;
end if;
end process p0;
end architecture dff_arch;

Method 2:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process is
begin
wait until (CLock = '1');
Q <= D;
Qbar <= not D;
end process p0;
end architecture dff_arch;

Method 3:( The most correct design)

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is 
begin

p0: process (Clock) is
variable state: std_logic;
begin

if rising_edge(Clock) then
state := D;
end if;
Q <= state;
Qbar <= not state;
end process p0; end architecture dff_arch;

Pin configuration is as follows:

1

Thank you.