VHDL components

7 segment up counter for DE0-Nano

In my previous post I have mentioned about the 7-segment display that I soldered for my DE0-Nano board. Now it’s time to get a simple program going in it. Here I will be implementing a up counter in the FPGA fabric. Conventional truth tables and karnaugh maps have been used to derive the logic for this simple task. Also in this demo you will understand how to develop a design module by module and how to combine them together using VHDL.