D-flip flip with Set and Reset

Following is the VHDL code for the design of a D-Flip flop with asynchronous set and reset functions. Normally Set and Reset is used to determine the initial state of a Flip flop in order to prevent it starting off with some arbitrary state.

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
begin
p0: process (Clock,Reset,Set) is
variable state: std_logic;
begin
	if (Reset = '0') then
	state := '0';
	elsif (Set = '0') then
	state := '1';
	elsif rising_edge(CLock) then
	state := D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

The same can be done using a signal instead of a variable as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity dff2 is
port (D, Clock, Reset, Set: in std_logic;
		Q, Qbar : out std_logic);
end entity dff2;

architecture dff2_arch of dff2 is
signal state: std_logic;
begin
p0: process (Clock,Reset,Set) is
begin
	if (Reset = '0') then
	state <= '0';
	elsif (Set = '0') then
	state <= '1';
	elsif rising_edge(CLock) then
	state <= D;
	end if;
	Q <= state;
	Qbar <= not state;
end process p0; 
end architecture dff2_arch;

Make sure you do the pin assignment correctly.

Thank you.

Programming a D-flip flop in VHDL

Following are few ways to code a positively edge triggered D Flip Flop in VHDL.

Method 1:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process (Clock) is
begin
if (Clock = '1') then
Q <= D;
Qbar <= not D;
end if;
end process p0;
end architecture dff_arch;

Method 2:

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is
begin
p0: process is
begin
wait until (CLock = '1');
Q <= D;
Qbar <= not D;
end process p0;
end architecture dff_arch;

Method 3:( The most correct design)

library IEEE;
use IEEE.std_logic_1164.all;

entity dff1 is
port (D, Clock : in std_logic;
		Q , Qbar : out std_logic);
end entity dff1;

architecture dff_arch of dff1 is 
begin

p0: process (Clock) is
variable state: std_logic;
begin

if rising_edge(Clock) then
state := D;
end if;
Q <= state;
Qbar <= not state;
end process p0; end architecture dff_arch;

Pin configuration is as follows:

Thank you.

Simple bit-shift example in VHDL

Here is another simple VHDL code to carryout simple bit shifting operation. I decided to post simple VHDL codes in this blog so that any newbie who reads this will be able to find some examples to work on. Make sure that you assign correct pins for inputs and outputs as mentioned in the

https://unboxnbeyond.wordpress.com/2013/03/24/hello-world-de0-nano-with-vhdl/#more-143

‘A’ should be connected to a push button
‘B’ should be connected to LEDs.

VHDL code:

library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;

entity bitshiftror is
port (A: in std_logic;
		B: out std_logic_vector(7 downto 0));
end entity bitshiftror;

architecture bitshiftor of bitshiftror is

signal B_out: BIT_VECTOR(7 downto 0) := (0 => '1', others => '0');
constant n: NATURAL := 1;

begin
aa: process (A) is
begin
	if((A xor '1') = '1') then
		B_out <= (B_out ror n);

		B <= to_stdlogicvector(B_out);				
	end if;
end process aa;
end architecture bitshiftor;

Thank you.

Hello world DE0-Nano with VHDL

Here i will be explaining how to write a very simple VHDL code to simulate an And gate with two inputs. In the following post I have mentioned about device families, pin assignments, compilation and programming the actual hardware. I will not repeat those information please go through this post if you have not.

Only difference here is that instead of adding Block diagram / Schematic to the project you should select File >New > VHDL file. Then you will get a window to type the code.

Following is the VHDL code,

entity VHDLturo is
port (A, B:in BIT;
Z : out BIT);
end VHDLturo;

architecture logicfunc of VHDLturo is
begin
Z <= A and B;
end architecture logicfunc;